`include "defines.v"

module id_reg(

    input                     clk,
    input                     rst,
    input                     id_stall_i,

    input  wire [`RAM_BUS]    id_pc_i,
    input  wire [31:0]        id_inst_i,
    input  wire [`REG_WIDTH]  id_op1_i,
    input  wire [`REG_WIDTH]  id_op2_i,
    input  wire [`REG_WIDTH]  id_imm_i,
    input  wire [5:0]         id_aluop_i,
    input  wire               id_skip_i,
    input  wire               id_ecall_i,
    input  wire               id_mret_i,

    input  wire               id_rd_w_ena_i,
    input  wire [`REG_BUS]    id_rd_w_addr_i,
    input  wire               id_csr_r_ena_i,
    input  wire               id_csr_w_ena_i,
    input  wire [11:0]        id_csr_addr_i,

    input  wire               id_reg_valid_i,

    output reg  [`RAM_BUS]    id_pc_o,
    output reg  [31:0]        id_inst_o,
    output reg  [`REG_WIDTH]  id_op1_o,
    output reg  [`REG_WIDTH]  id_op2_o,
    output reg  [`REG_WIDTH]  id_imm_o,
    output reg  [5:0]         id_aluop_o,
    output reg                id_skip_o,
    output reg                id_ecall_o,
    output reg                id_mret_o,
    
    output reg                id_rd_w_ena_o,
    output reg  [`REG_BUS]    id_rd_w_addr_o,
    output reg                id_csr_r_ena_o,
    output reg                id_csr_w_ena_o,
    output reg  [11:0]        id_csr_addr_o,

    output reg                id_reg_valid_o

);


    always@(posedge clk)begin
        if(rst == `RST )begin
            id_pc_o         <= 0;
            id_inst_o       <= 0;
            id_op1_o        <= 0;
            id_op2_o        <= 0;
            id_imm_o        <= 0;
            id_aluop_o      <= 0;
            id_skip_o       <= 0;
            id_ecall_o      <= 0;
            id_mret_o       <= 0;
            id_rd_w_ena_o   <= 0;
            id_rd_w_addr_o  <= 0;
            id_csr_r_ena_o  <= 0;
            id_csr_w_ena_o  <= 0;
            id_csr_addr_o   <= 0;
            id_reg_valid_o  <= 0;
        end
        else if(id_stall_i)begin
            id_pc_o         <= id_pc_o;
            id_inst_o       <= id_inst_o;
            id_op1_o        <= id_op1_o;
            id_op2_o        <= id_op2_o;
            id_imm_o        <= id_imm_o;
            id_aluop_o      <= id_aluop_o;
            id_skip_o       <= id_skip_o;
            id_ecall_o      <= id_ecall_o;
            id_mret_o       <= id_mret_o;
            id_rd_w_ena_o   <= id_rd_w_ena_o;
            id_rd_w_addr_o  <= id_rd_w_addr_o;
            id_csr_r_ena_o  <= id_csr_r_ena_o;
            id_csr_w_ena_o  <= id_csr_w_ena_o;
            id_csr_addr_o   <= id_csr_addr_o;
            id_reg_valid_o  <= id_reg_valid_o;
        end
        else begin
            id_pc_o         <= id_pc_i;
            id_inst_o       <= id_inst_i;
            id_op1_o        <= id_op1_i;
            id_op2_o        <= id_op2_i;
            id_imm_o        <= id_imm_i;
            id_aluop_o      <= id_aluop_i;
            id_skip_o       <= id_skip_i;
            id_ecall_o      <= id_ecall_i;
            id_mret_o       <= id_mret_i;
            id_rd_w_ena_o   <= id_rd_w_ena_i;
            id_rd_w_addr_o  <= id_rd_w_addr_i;
            id_csr_r_ena_o  <= id_csr_r_ena_i;
            id_csr_w_ena_o  <= id_csr_w_ena_i;
            id_csr_addr_o   <= id_csr_addr_i;
            id_reg_valid_o  <= id_reg_valid_i;
        end
    end




endmodule